(1) Field of the Invention
The present invention relates to a time switch control system, and more particularly, to a time switch control system used for digital time-division multiplex communications and having a cross-connect function for exchanging time-slot signals input thereto from a plurality of channels within the channels in accordance with channel setting information.
(2) Description of the Related Art
Recent transmission systems and the like adapted for digital time-division multiplex communications have a cross-connect function to achieve effective use of channels. The cross-connect function permits a plurality of time-slot signals input from a plurality of channels to be exchanged within the channels for output, whereby multiposition switching, as well as flexible use of channels such as the setting of a number of channels according to traffic etc., is available, thus permitting effective use of the channels. To achieve the cross-connection function, a time switch (TSW) must be provided as an indispensable element.
Referring to FIG. 1, the arrangement and operation of a conventional time switch (TSW) will be explained. In FIG. 1, (A) shows the arrangement of a conventional time switch, (B) shows input signals to the time switch, and (C) shows output signals from the time switch.
A data memory (DM) 91 is supplied with input signals In#1 to In#n from n channels. As shown in FIG. 1(B), the input signals In#1 to In#n are each composed of, e.g., four time-slot signals per cycle, and the data memory (DM) 91 sequentially stores all of the four time-slot signals from the individual channels in accordance with the addressing of a DM write address counter (DMAD CNTR) 92.
A control memory (CM) 93 stores channel setting information. The channel setting information is given as a command from the operating system of a work station or the like, and comprises address information indicating how the input time-slot signals should be exchanged. The control memory (CM) 93 supplies the channel setting information to the data memory (DM) 91 in accordance with the addressing from a CM read address counter (CMAD CNTR) 94, and the data memory (DM) 91 reads out the input time-slot signals stored therein and supplies the same to m channels as output signals Out#1 to Out#m in accordance with the channel setting information supplied thereto. The output signals Out#1 to Out#m are shown in FIG. 1(C). Reading and outputting the input time-slot signals in accordance with the channel setting information means that the time-slot signals are eventually exchanged. In (B) and (C) of FIG. 1, numbers in the squares represent time-slot numbers, and symbol "-" in the squares indicates that there is no time-slot signal to be output, i.e., an unconnected state of the channel concerned, because of the absence of a channel setting.
In the conventional time switch described above, all of the input time-slot signals are sequentially stored in the data memory (DM) 91. Thus, the stored time-slot signals may include those which are not actually output, depending on the channel setting, and this means that some area of the data memory (DM) 91 is occupied by unnecessary time-slot signals.
This will be explained with reference to FIG. 1. Comparison between the output signals shown in (C) and the input signals shown in (B) reveals that the five time-slot signals 12, 21, 24, n3 and n4 are not output, and thus are useless signals which need not be stored in the data memory (DM) 91.
In the case where an SRAM is used for the data memory (DM) 91, for example, power consumed in an operation mode in which data is retained is on the order of 10 to 100 mW, whereas power consumed in the standby mode, in which data is not retained, is on the order of .mu.W. Thus, if useless time-slot signals are excluded from the data memory (DM) 91, the power consumption can be greatly cut down.
Meanwhile, a time-slot exchange circuit requires a large-capacity memory because all of the input time-slot signals are temporarily stored before being exchanged. In this regard, Unexamined Japanese Patent Publication (KOKAI) No. 3-92027 discloses a circuit in which, among input time-slot signals, only those which are to be exchanged are stored to thereby reduce the required memory capacity. However, this circuit is not designed to achieve the cross-connect function by which time-slot signals are exchanged among a plurality of channels; it is designed to merely transpose time-slot signals within the same channel, to be more specific, it is designed to temporarily store a predetermined time-slot signal selected among input time-slot signals and then insert the stored time-slot signal into the input time-slot signals. Furthermore, the circuit is not constructed such that some of input time-slot signals which are not actually output are prevented from being stored.